1. Field of the Invention
Example embodiments of the present invention relate to a refresh control circuit for performing a refresh operation to preserve data stored in memory cells and a semiconductor memory device having the same.
2. Description of the Related Art
In a semiconductor memory device such as Dynamic Random Access Memory (DRAM), a refresh operation of detecting and amplifying data stored in memory cells and rewriting the data in the memory cells may be performed at regular intervals. Through such a refresh operation, data stored in memory cells can be preserved. Semiconductor memory devices requiring such refresh operations as described above generally include refresh control circuits.
In a semiconductor memory device, a specific memory cell may have degraded refresh characteristics relative to other memory cells due to imbalance in a manufacturing process or the imbalance and/or insufficiency of material. Such a degraded memory cell requires a shorter refresh interval than normal memory cells.
FIG. 1 is a diagram illustrating a conventional refresh control circuit 10 and a semiconductor memory device having the same. The refresh control circuit 10 may operate to sequentially select the rows of a memory bank MBANK and activate word lines WL corresponding to selected rows, in response to the activation of a refresh trigger signal PRFH. Conventionally, the refresh trigger signal PRFH is a signal activated at intervals and is provided by a refresh trigger circuit 20. An address counter 11 may generate sequentially variable counting address CNT<1:n> in response to the activation of the refresh trigger signal PRFH. Furthermore, a row decoder 13 may decode the counting address CNT<1:n>, select a row of a memory bank MBANK, and activate the word line of the selected row.
In accordance with the conventional refresh control circuit 10 shown in FIG. 1, all the memory cells included in a single memory bank MBANK are refreshed at the same refresh interval. For example, as shown in FIG. 2, assume that at least one degraded memory cell MCi is present in a memory bank MBANK. According to this conventional example, a refresh interval for the memory bank MBANK is determined based on the degraded memory cell MCi. Assuming the refresh interval required for the degraded memory cell MCi is 128 ms and the refresh interval required for the other memory cells is 256 ms, the refresh interval for the conventional semiconductor memory device is set to 128 ms. That is, for the memory cells other than the degraded memory cell MCi, the refresh interval is set to 128 ms on the basis of the degraded memory cell MCi even though the refresh interval could be set to 256 ms.
Accordingly, in a semiconductor memory device having a conventional refresh control circuit 10, the refresh interval is inefficiently set, so that excessive power is consumed due to the repetition of an unnecessary operation, thereby incurring the degradation of characteristics of a DRAM.